Designing an asynchronous processor using Petri nets

Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets

Abstract. This paper approaches the problem of synthesising an asynchronous control circuit for a stage of the Sproull Counterflow pipeline processor (CFPP) as an exercise in exploiting formal techniques available for Petri nets. We first synthesise a Petri net model of the CFPP stage control from its original “five-state-five-event” description due to Charles Molnar. Secondly, we implement tha...

Designing Control Logic for Counterrow Pipeline Processor Using Petri Nets

This paper approaches the problem of implementing an asynchronous control for a stage of the Sproull Counterrow pipeline processor (CFPP) as an exercise in combining two synthesis techniques recently developed for Petri nets. We rst synthesise a number of Petri net models of the CFPP stage control from its original \\ve-state-ve-event" description due to C. Molnar. Secondly, we implement these ...

Synthesis of Asynchronous Hardware from Petri Nets

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits...

Hardware and Petri Nets: Application to Asynchronous Circuit Design

Asynchronous circuits is a discipline in which the theory of concurrency is applied to hardware design. This paper presents an overview of a design framework in which Petri nets are used as the main behavioral model for speciication. Techniques for synthesis, analysis and formal veriication of asynchronous circuits are reviewed and discussed.

Designing Control Logic for Counter ow Pipeline Processor Using Petri Nets